A typical conventional solid-state imaging device will be described with reference to FIG. 10. This solid-state imaging device includes a plurality of photosensitive cells 30 arranged in a matrix and a peripheral driving circuit for driving the photosensitive cells 30. Each of the photosensitive cells 30 includes a photodiode 31 for converting incident light into an electric charge, a transfer transistor 32, an amplifier transistor 33, and a reset transistor 34. On the other hand, the peripheral driving circuit includes a vertical driver circuit 36 for extracting electric charges of the plurality of photosensitive cells 30 to a vertical signal line 35 as pixel signals, a noise suppressing circuit 37 for suppressing noise in the pixel signals extracted from the plurality of photosensitive cells 30, a horizontal transistor group 38 for controlling the output of the pixel signals from the noise suppressing circuit 37, a horizontal driver circuit 39 for driving the horizontal transistor group 38, and a load transistor group 40 (see Non-patent Document 1, for example).
A gate electrode of the transfer transistor 32 is connected to the vertical driver circuit 36 via a transfer control signal line 41. The transfer transistor 32 transfers a signal charge generated by the photodiode 31 to a gate electrode of an amplifier transistor 33 in accordance with a transfer control signal from the vertical driver circuit 36. Structurally, a source region of the transfer transistor 32 is formed of a part of the photodiode 31.
A source of the amplifier transistor 33 is connected to a source of a load transistor 40a and the noise suppressing circuit 37 via the vertical signal line 35. A drain of the amplifier transistor 33 is connected to a drain line 42. The amplifier transistor 33 sends a pixel signal to the vertical signal line 35 in accordance with a potential based on the signal charge input to the gate electrode from the transfer transistor 32. Due to the use of the amplifier transistor 33 as a source follower, the pixel signal sent to the vertical signal line 35 is amplified with a different amplification factor depending on the potential of the gate electrode of the amplifier transistor 33.
A gate electrode of the reset transistor 34 is connected to the vertical driver circuit 36 via a reset signal line 43. A source of the reset transistor 34 is connected to a drain of the transfer transistor 32 and the gate electrode of the amplifier transistor 33. A drain region of the reset transistor 34 is connected to the drain line 42. The reset transistor 34 resets a potential of the drain of the transfer transistor 32, i.e., the potential of the gate electrode of the amplifier transistor 33, to a predetermined initial value in accordance with a reset signal from the vertical driver circuit 36.
A drain of the load transistor 40a is connected to a load (constant current source) via wiring 44. A gate electrode of the load transistor 40a is connected to a control signal line 45 for controlling the connection between the vertical signal line 35 and the load.
The output of the noise suppressing circuit 37 is transmitted to a horizontal signal line 46 via a horizontal transistor 38a constituting the horizontal transistor group 38.
In this solid-state imaging device, when the characteristics such as a threshold voltage of the amplifier transistors 33 included in the respective plurality of photosensitive cells 30 vary, fixed pattern noise appears in the pixel signals on the vertical signal line 35. The noise suppressing circuit 37 is provided to suppress the fixed pattern noise.
FIG. 11 shows one of the photosensitive cells 30 and a specific configuration of an equivalent circuit of the noise suppressing circuit 37 connected to the photosensitive cell 30. The noise suppressing circuit 37 includes a transistor 50, a large-capacitance capacitor 51 formed on a semiconductor substrate as an element having an MIM (Metal Insulator Metal) structure, a DMOS (Double-diffused MOS) structure or the like, a clamping transistor 52, and a capacitor 53 formed as an element like the capacitor 51. FIG. 11 shows the case where the load transistor 40a is in an ON state and the drain of the amplifier transistor 33 is grounded via a constant current source (load) 54.
An operation of the solid-state imaging device having the above-mentioned configuration will be described with reference to FIG. 11.
(Operation A) Initially, a potential at a node 55, i.e., the potential of the drain region (floating diffusion) of the transfer transistor 32 and the gate electrode of the amplifier transistor 33, is reset to a predetermined potential VDD. At this time, a potential V1 of the vertical signal line 35 (node 56) is expressed as follows.V1=VDD−VGS  (1)In Formula 1, VGS represents a constant value determined depending on an operating point.
(Operation B) Then, the clamping transistor 52 is turned ON, and a potential at a node 57 is set to VDD. Holding the potential of the node 57 to be a potential of VDD, the transistor 50 is turned ON. This allows the capacitor 51 to be charged. A final electric charge Q to be accumulated in the capacitor 51 is expressed as follows.Q=C1(VDD−V1)  (2)In Formula 2, C1 represents a capacitance of the capacitor 51.
(Operation C) Then, the clamping transistor 52 is turned OFF. Here, the transistor 50 remains in an ON state.
(Operation D) Then, the transfer transistor 32 is turned ON, and an electric charge Q1 generated by the photodiode 31 is transferred to the drain region of the transfer transistor 32. As a result, the potential at the node 55 becomes a potential VG corresponding to the electric charge Q1. The potential VG is expressed as follows in accordance with a parasitic capacitance (capacitance accompanying the floating diffusion) C of the transfer transistor 32: VG=VDD−Q1/C. Accordingly, a potential V2 of the vertical signal line 35 is expressed as follows.V2=VG−VGS=VDD−Q1/C−VGS  (3)
The electric charge Q accumulated in the capacitor 51 is distributed to the capacitor 51 and the capacitor 53 in accordance with their capacitances. Defining that the potential at the node 57 is Vout, Vout is equal to the solutions of the following simultaneous equations.C1(Vout−V2)=Q+ΔQ  (4)C2×Vout=−ΔQ  (5)In Formula 5, C2 represents a capacitance of the capacitor 53. As a result of solving the above simultaneous equations, Vout is expressed as follows.Vout=C1/(C1+C2)×(VDD−Q1/C)  (6)This state is maintained until the potential at the node 57 is stabilized at Vout.
(Operation E) Then, in the state where the potential at the node 57 is Vout, the horizontal transistor 38a is turned ON based on a horizontal control signal from the horizontal driver circuit 39. As a result, the potential Vout is transmitted to the horizontal signal line 46, and a voltage corresponding to Vout is output via an amplifier 58. In other words, a voltage that varies depending on the electric charge Q1 generated by the photodiode 31 is output as an image signal.
In general, the characteristics such as a threshold voltage of all the amplifier transistors 33 formed for the respective photosensitive cells 30 are not always uniform. Accordingly, fixed pattern noise appears in the pixel signal of the potential V2 on the vertical signal line 35. However, with the noise suppressing circuit 37, the pixel signal of the potential Vout that has passed through the noise suppressing circuit 37 does not include a member (VGS) dependent on variations in the characteristics of the amplifier transistor 33, and thus is free from an influence of fixed pattern noise.
As described above, it is required that the signal potential be held at the node 57 from the moment the potential at the node 55 is reset to VDD until the pixel signal is output to the horizontal signal line 46 via the horizontal transistor 38a (during the period between Operation B and Operation D). Unless the signal potential at the node 57 is held, a malfunction occurs in the noise suppressing circuits 37. More specifically, the image signals corresponding to all the photosensitive cells 30 connected to the single vertical signal line 35 have voltages different from the voltage of the signal in accordance with the electric charge Q1 generated by the photosensitive cells 30. In the case of an image display based on such image signals, display defects occur in an entire single vertical row of pixels, and the defective displays in a vertical line are observed in the image.
As described above, in the solid-state imaging device in which each of the photosensitive cells 30 has the amplifier transistor 33 and the peripheral driving circuit has the noise suppressing circuit 37, it is particularly important to suppress a leakage of current in the clamping transistor 52 in the noise suppressing circuit 37 that has to hold the transmitted signal potential for a predetermined period of time.
In general, a leakage of current in a transistor generally is divided into a pn-junction opposite-direction leakage and an off leakage. In recent years, as transistors become smaller, a GIDL (gate induced drain leakage), which is a kind of off leakage, has become a particular problem.
Hereinafter, the GIDL will be described. FIG. 12 is a schematic cross-sectional view partially showing a structure of a MOS transistor for explaining the GIDL. FIG. 12 shows a part of an n-channel transistor from a gate electrode to a drain region. A drain region 61 is formed on a surface region of a semiconductor substrate 60, and a gate electrode 63 is formed on a top surface via a gate oxide film 62. On an end face of the gate oxide film 62 and the gate electrode 63, a sidewall spacer 64 is provided.
As shown in FIG. 12, there is an overlapping region 65 between the gate electrode 63 and the drain region 61. In the overlapping region 65, when an electric field that allows a positive hole to be accumulated on a semiconductor substrate 60 side is applied between the gate electrode 63 and the drain region 61 via the gate oxide film 62, a conduction type on a surface of the drain region 61 is converted into a p-type by the action of the electric field, and a valence band level is developed in the overlapping region 65. As a result, a band-to-band tunnel current is generated between the valence band level developed in the overlapping region 65 and a conduction band level on a drain region 61 side, and this current becomes a substrate current (indicated by an arrow 66 in FIG. 12). The current leakage thus occurring is referred to as a GIDL.
Further, in recent years, as transistors in a solid-state imaging device become smaller, it is becoming popular to form a refractory metal silicide layer on a surface of diffusion layers constituting a source region and a drain region, respectively, of a MOS transistor by using a salicide process, so as to reduce the resistance of the respective diffusion layers of the source region and the drain region. In such a case, the GIDL is reported to be remarkable (see Non-patent Document 2, for example).
Non-patent Document 1: Basics and Applications of CCD/CMOS Image Sensor, CQ Publishing Co., Ltd., Pages 175-176
Non-patent Document 2: Woo-Tag Kang et al.: IEEE, Electron Device Lett. 21, 9, 2000